Conventional high bandwidth memory systems are used for demanding image processing applications such as real time video encoding. A worst case memory latency and bandwidth must meet the criteria of a video encoding system since dropped frames cannot be tolerated. Recent high definition video encoding and high efficiency encoding systems, such as the H.264 standard, are dramatically increasing the worst case bandwidth specifications. In conventional real time systems, external dynamic random access memory (DRAM) chips provide a full worst case bandwidth for the real time video encoding. Conventional on-chip caches, that provide sufficient bandwidth and latency when hitting the cache, do not provide sufficient worst case performance when missing the cache. As a result, power consumption of advanced real time video processing circuits are excessive for portable applications.